Know ATS Score
CV/Résumé Score
  • Expertini Resume Scoring: Our Semantic Matching Algorithm evaluates your CV/Résumé before you apply for this job role: Senior Staff Silicon Design Verification Engineer.
Malaysia Jobs Expertini

Urgent! Senior Staff Silicon Design Verification Engineer Job Opening In Bayan Lepas – Now Hiring AMD

Senior Staff Silicon Design Verification Engineer



Job description

Senior Staff Silicon Design Verification Engineer

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s GPU IP, resulting in no bugs in the final design.

The Person

  • You have a passion for modern CPU or GPU architecture, digital design, and verification in general.

  • You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones.

  • You have strong analytical and problem‑solving skills and are willing to learn and ready to take on problems.

Key Responsibilities

  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.

  • Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.

  • Build testbench and develop the Testbench component with UVM.

  • Estimate the time required to write the new feature tests and any required changes to the test environment.

  • Build the directed and random verification tests.

  • Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.

  • Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.

Preferred Experience

  • Proficient in IP level ASIC verification.

  • Proficient in debugging firmware and RTL code using simulation tools.

  • Proficient in using UVM testbenches and working in Linux and Windows environments.

  • Experienced with Verilog, SystemVerilog, SVA, C, and C++.

  • Developing UVM based verification frameworks and testbenches, processes and flows.

  • Good understanding and hands‑on experience in the UVM concepts and SystemVerilog language.

  • Scripting language experience: Perl, Ruby, Makefile, shell preferred.

Academic Credentials

  • Bachelors or Masters degree in Computer Engineering or Electrical Engineering.

#J-18808-Ljbffr


Required Skill Profession

Engineering



Your Complete Job Search Toolkit

✨ Smart • Intelligent • Private • Secure

Start Using Our Tools

Join thousands of professionals who've advanced their careers with our platform

Rate or Report This Job
If you feel this job is inaccurate or spam kindly report to us using below form.
Please Note: This is NOT a job application form.


    Unlock Your Senior Staff Potential: Insight & Career Growth Guide