Silicon Design Engineer (ASIC & STA)

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems.

Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary.

When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.

Join us as we shape the future of AI and beyond.

Together, we advance your career.

THE ROLE: In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs.

You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.

THE PERSON: You are passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies.

You enjoy solving challenging problems, are detail-oriented, and thrive in a collaborative team environment and passionate to work with vibrant team located in different time zone .

With strong analytical skills and a methodical approach, you are eager to learn, share knowledge, and contribute to building cutting-edge silicon.

KEY RESPONSIBILITIES: Develop and implement power reduction strategies across SoC/IP design.

Perform synthesis and static timing analysis (STA) to achieve PPA targets.

Analyze and optimize dynamic and leakage power using industry-standard tools.

Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.

Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.

Support sign-off activities for Lint , CDC , synthesis, timing, and power closure.

Automate and streamline power and timing workflows to improve efficiency.

Build test plan documentation, accounting for interactions with other features, the hardware.

PREFERRED EXPERIENCE: Strong background in ASIC synthesis and static timing analysis (STA).

Hands-on expertise with EDA tools such as Synopsys Design Compiler, PrimeTime, PrimePower, Power Artists , or equivalent.

Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).

Familiarity with UPF/CPF power intent specification and verification.

Solid understanding of digital design fundamentals, RTL coding (Verilog/SystemVerilog).

Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm) is a strong plus.

Proficiency in scripting languages (TCL, Perl, Python, or Shell) for flow automation.

Exposure to floorplanning, place-and-route, and ECO flows is desirable.

Knowledge of low-power design methodologies and trade-offs.

Prior leadership, mentorship, or cross-functional collaboration experience is an asset.

Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Automating workflows in a distributed compute environment.

ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering.

LOCATION: Penang, Malaysia #LI-SJ1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.THE ROLE: In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs.

You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.

THE PERSON: You are passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies.

You enjoy solving challenging problems, are detail-oriented, and thrive in a collaborative team environment and passionate to work with vibrant team located in different time zone .

With strong analytical skills and a methodical approach, you are eager to learn, share knowledge, and contribute to building cutting-edge silicon.

KEY RESPONSIBILITIES: Develop and implement power reduction strategies across SoC/IP design.

Perform synthesis and static timing analysis (STA) to achieve PPA targets.

Analyze and optimize dynamic and leakage power using industry-standard tools.

Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.

Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.

Support sign-off activities for Lint , CDC , synthesis, timing, and power closure.

Automate and streamline power and timing workflows to improve efficiency.

Build test plan documentation, accounting for interactions with other features, the hardware.

PREFERRED EXPERIENCE: Strong background in ASIC synthesis and static timing analysis (STA).

Hands-on expertise with EDA tools such as Synopsys Design Compiler, PrimeTime, PrimePower, Power Artists , or equivalent.

Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).

Familiarity with UPF/CPF power intent specification and verification.

Solid understanding of digital design fundamentals, RTL coding (Verilog/SystemVerilog).

Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm) is a strong plus.

Proficiency in scripting languages (TCL, Perl, Python, or Shell) for flow automation.

Exposure to floorplanning, place-and-route, and ECO flows is desirable.

Knowledge of low-power design methodologies and trade-offs.

Prior leadership, mentorship, or cross-functional collaboration experience is an asset.

Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Automating workflows in a distributed compute environment.

ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering.

LOCATION: Penang, Malaysia #LI-SJ1 #LI-Hybrid
Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Required Skill Profession

Engineers